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FPGA-Based New Hybrid Adder Design with the Optimal Bit-Width Configuration

dc.contributor.authorAlshewimy , Mahmoud A.M.
dc.contributor.authorSERTBAŞ, AHMET
dc.date.accessioned2021-03-05T10:43:43Z
dc.date.available2021-03-05T10:43:43Z
dc.date.issued2013
dc.identifier.citationAlshewimy M. A. , SERTBAŞ A., "FPGA-Based New Hybrid Adder Design with the Optimal Bit-Width Configuration", International Journal of Computer Applications, cilt.65, ss.15-19, 2013
dc.identifier.othervv_1032021
dc.identifier.otherav_a4a3b40e-d34f-42b8-94b9-848481d9e222
dc.identifier.urihttp://hdl.handle.net/20.500.12627/110134
dc.identifier.urihttp://www.ijcaonline.org/archives/volume65/number11/10968-6100
dc.language.isoeng
dc.subjectBilgisayar Bilimi
dc.subjectMühendislik ve Teknoloji
dc.subjectMühendislik, Bilişim ve Teknoloji (ENG)
dc.subjectBilgisayar Bilimleri
dc.titleFPGA-Based New Hybrid Adder Design with the Optimal Bit-Width Configuration
dc.typeMakale
dc.relation.journalInternational Journal of Computer Applications
dc.contributor.departmentDiğer Kurumlar , ,
dc.identifier.volume65
dc.identifier.issue11
dc.identifier.startpage15
dc.identifier.endpage19
dc.contributor.firstauthorID467249


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